Memory devices find ubiquitous use in electronic devices. Many electronic devices employ volatile memory devices, which provides relatively large amount of storage space for a low cost, and provides faster access to data compared to typical nonvolatile memory options. However, the volatile nature of volatile memory requires refreshing the memory devices to retain the data. Refreshing memory devices continues to take a large percentage of overall memory bandwidth. For example, with an 8 Gb LPDDR3 (low power dual data rate, version 3) DRAM (dynamic random access memory) die can take up approximately 5.38% of overall bandwidth as a refresh command has to be sent every 3.9 us (tREFI, refresh interval time) and each refresh command takes 210 ns (tRFC, time between refresh commands) to complete (210 ns/3.9 us=5.38%). The tRFC on a 16 Gb device tRFC value is expected to almost double, which would indicate that future memory devices are at risk of using up more (e.g., up to approximately 10%) total bandwidth in refresh. The more bandwidth a memory device uses in refresh, the less it has for processing data access commands (read or write), which can degrade memory subsystem performance.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein.